Nasdaq

Cadence Accelerates Cloud Hyperscale Infrastructure with Third-Generation 112G-LR SerDes IP on TSMC’s N5 Process

DSP-based, flex-rate multi-rate SerDes IP is optimized for PPA for next-generation compute, switching, storage, AI/ML and 5G SoCs New architecture offers 25% power improvement, 40% area reduction and ...
Semiconductor Engineering

Enabling Integration Success Using High-Speed SerDes IP

Internet traffic volumes continue to grow at a breakneck pace, and the demands on SerDes speeds increase accordingly. High-speed SerDes play an integral part of the networking chain and these speed ...
Nasdaq

Cadence Expands Design IP Portfolio with 56G Long-Reach PAM4 SerDes on TSMC N7 and N6 Processes

DSP-based, multi-rate SerDes IP is optimized for power, performance and area for next-generation 5G and AI/ML SoC design Cadence is ready to engage with customers immediately on 5G, compute server ...
Business Wire

Rambus Announces Tapeout and Availability of 112G Long Reach SerDes PHY on Leading-edge 7nm Node for High-Performance Communications and Data Centers

SUNNYVALE, Calif.--(BUSINESS WIRE)--Today Rambus Inc. (NASDAQ: RMBS) announced its newest portfolio solution of 112G Long Reach (LR) SerDes PHY on a leading-edge 7nm process node for next-generation ...
Semiconductor Engineering

The Challenges Of Designing 28G And 56G SerDes IP

The industry move to 56 Gbps PAM4 is undoubtedly one of the greatest challenges currently facing SerDes IP designers and their customers. To begin with, shifting to 56 Gbps PAM4 immediately causes a ...
Design-Reuse

LogicVision and DA-Test Collaborate to Provide Low Cost High Speed SerDes I/O Test

SAN JOSE, Calif. — August 8, 2006 — LogicVision, Inc. (NASDAQ: LGVN), a leading provider of semiconductor test and yield learning solutions, today announced a successful collaboration with DA-Test ...
EDN

DESIGN TOOLS: Signal integrity tool enhances serdes support

Santa Cruz, Calif. — Many pc-board designers are turning to serial/deserializer (serdes) interconnects, which can allow signaling between components of up to 10 Gbits/second. But there has been a ...
EDN

HyperLynx update supports serdes design

SANTA CRUZ, Calif. — New capabilities in Mentor Graphics' HyperLynx signal integrity product will help facilitate pc-board designs that use serial/deserializer (serdes) interconnects, according to the ...
Electronic Design

White Papers: Custom ADC at CERN | 6 SERDES Design & Verification Challenges | More

Electronic Design is dedicated to keeping design engineers informed of the latest advancements in the engineering community. As such, we thought you would have interest in these resources from Mentor ...
Electronic Design

Latest SERDES Lowers the Bar in Current Consumption

London, England: Fairchild launched its second-generation FIN324C SerDes-uLP (Ultra Low Power) series with claims that it offers the industry’s lowest current consumption (~4mA at 5.44MHz). The ...
Business Wire

Cadence Accelerates Cloud Hyperscale Infrastructure with Third-Generation 112G-LR SerDes IP on TSMC’s N5 Process

SAN JOSE, Calif.--(BUSINESS WIRE)--Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process for hyperscale ASICs, ...